input a,b,c,d;
input clk,res;
output led1,led2,led3,led4;
reg led1,led2,led3,led4;
reg k;
always @(clk)
begin
if(res==0)
begin
led1<=0;
led2<=0;
led3<=0;
led4<=0;
k<=0;
end
else
begin
if(k==0)
begin
if(a)
begin
led1<=1;
k<=1;
end
else
if(b)
begin
led2<=1;
k<=1;
end
else
if(c)
begin
led3<=1;
k<=1;
end
if(d)
begin
led4<=1;
k<=1;
end
end
end
end
endmodule