use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fp40 is
port( rst: in std_logic;
clk: in std_logic;
fpclk: out std_logic);
end fp40;
architecture arc of fp40 is
begin
process(clk)
variable count: integer range 0 to 30;
variable clk0: std_logic;
begin
if rst='0' then
clk0<='0' ;
elsif clk'event and clk='0' then
if count=30 then
clk0:=not clk0;
count:=0;
else
count:=count+1;
end if;
end if;
fpclk<=clk0;
end process;
end arc;
rst為低時候復位信號有效，此時輸出為0！