use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dynamic is
Port ( clk : in std_logic;
reset: in std_logic;
din1 : in std_logic_vector(6 downto 0); --譯碼後的數據信號1
din2 : in std_logic_vector(6 downto 0); --譯碼後的數據信號2
din3 : in std_logic_vector(6 downto 0); --譯碼後的數據信號3
din4 : in std_logic_vector(6 downto 0); --譯碼後的數據信號4
shift: out std_logic_vector(3 downto 0); --位選信號
bus4 : out std_logic_vector(6 downto 0)); --數據信號
end dynamic;
architecture Behavioral of dynamic is
signal scan_clk:std_logic_vector(1 downto 0);
begin
process(clk,scan_clk,reset) --分頻進程
variable scan:std_logic_vector(17 downto 0);
begin
if reset='1' then
scan:="000000000000000000";
scan_clk<="00";
elsif clk'event and clk='1'then
scan:=scan+1;
end if;
scan_clk<=scan(17 downto 16);
end process;
process(scan_clk,din1,din2,din3,din4) --掃描進程
begin
case scan_clk is
when "00"=>
bus4<=din1;
shift<="0001";
when "01"=>
bus4<=din2;
shift<="0010";
when "10"=>
bus4<=din3;
shift<="0100";
when "11"=>
bus4<=din4;
shift<="1000";
when others=> bus4<="0000000";shift<="0000";
end case;
end process;
end Behavioral;