use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity minutes is
Port ( rst3,selector2,ky_2j : in STD_LOGIC;
B10 : in std_logic;
C : out std_logic;
dat30 : out std_logic_vector(7 downto 0));
end minutes;
architecture Behavioral of minutes is
signal dat31,dat32 : std_logic_vector(7 downto 0):=(others =>'0');
begin
process(rst3,B10,ky_2j)
begin
case selector2 is
when '1' =>dat32<=dat31; if ky_2j'event and ky_2j='1' then
if dat31(7 downto 4)="0101" and dat31(3 downto 0)="1001"
then dat31(7 downto 0)<="00000000";
elsif dat31(3 downto 0)<"1001" then dat31(3 downto 0)<=dat31(3 downto 0)+1;
else dat31(3 downto 0)<="0000";
if dat31(7 downto 4)<"0101" then dat31(7 downto 4)<=dat31(7 downto 4)+1;
else dat31(7 downto 4)<="0000";
end if ;
end if ;
end if ;
dat30<=dat31;
when '0' =>dat31<=dat32; if(rst3 = '0') then dat32<=(others =>'0');
elsif B10'event and B10='1' then
if dat32(7 downto 4)="0101" and dat32(3 downto 0)="1001"
then C<='1'; dat32(7 downto 0)<="00000000";
else C<='0';
if dat32(3 downto 0)<"1001" then dat32(3 downto 0)<=dat32(3 downto 0)+1;
else dat32(3 downto 0)<="0000";
if dat32(7 downto 4)<"0101" then dat32(7 downto 4)<=dat32(7 downto 4)+1;
else dat32(7 downto 4)<="0000";
end if;
end if;
end if;
end if;
dat30<=dat32;
when others =>null;
end case;
end process;
end Behavioral;