This design using FPGA parallel architecture, computing speed of the characteristics and reliability characteristics of high-speed USB2.0 interface, designed a FPGA + USB2.0 + computer FIR digital filter system, FPGA's speed and machine flexibility of Computer organically through the USB2.0 bus, combined block diagram shown in Figure 3. On the one hand, the computer will calculate the configuration parameters transmitted to the next through the USB2.0 bus, FPGA, in order to achieve different windows, different cut-off frequency of the FIR filter. On the other hand, use 10-bit A / D converter for signal conversion, digital signal input to the FPGA device, in the FPGA devices for FIR filtering, the filtered data through USB2.0 Bus Transfer to the machine operator machine.
2,1 A / D converter module
A / D converter module main function is to digitize the analog signal, and then into the FPGA in digital signal processing. A / D converter module structure shown in Figure 4, the first analog signals for signal conditioning, and then A / D converter in FPGA will be under the control of signal conditioning to convert a digital signal, power supply module for the chip provides 5V and 3.3V power.
2.1.1 Signal Conditioning Circuit
System uses the A / D conversion chip analog input signal peak-peak voltage of +2 V, for some of the output analog signal range does not comply with the A / D conversion chip requirements, in order to expand the application of the system, and therefore A / D conversion before the signal conditioning. Conditioning is the amplification, buffering, or calibration of analog signals to make it suitable for analog / digital converter (ADC) input. The key is to choose the op-amp.
The design of signal conditioning circuit for two voltage-follower circuits, using low-power voltage feedback amplifier AD8052. Signal conditioning circuit in Figure 5. The amplifier input voltage range-0.2V ~ 4V. 8-pin voltage, using a single +5 V power supply to work properly. Input signal for the Signal, according to the diagram of the circuit connection, the output voltage range of the signal AD Sigin enables A / D conversion chip work correctly.
2.1.2 A / D conversion circuit
A / D conversion circuit according to pre-selected sampling period, the input to the system's analog signal is collected. Taking into account the need for system flexibility and future upgrades, the design of A / D conversion chip to use to use 10-bit accuracy, sampling rate as low as 20kHz, up to 40MHz of the AD9203 chip.
AD9203 is a AD's buy one single, low-voltage high-speed A / D conversion chip. It is stable and reliable accuracy in the whole sample within the bandwidth, and always remained a 10-bit precision; in 40MHz sampling rate, the effective number of bits still to reach 9.55, the differential non-linearity of ± 0.25 LSB, SNR and distortion remain at around 59dB. AD9203 operating voltage more flexible, allowing changes in the context of 2.7V ~ 3.6V, especially suitable for portable devices at low voltage, high-speed operation. A / D circuit shown in Figure 6. Analog signal ADSigin from 25 feet input, the conversion provided by the FPGA clock ADCLK from 15 feet input, converted 10-bit digital signal ADD0 ~ ADD9 from 3 to 12 feet out to the FPGA, the FPGA in digital signal processing.
2.2 Power Supply Circuit
As the external power supply voltage of 5V, while the A / D conversion chip AD9203 operating voltage and the FPGA's I / O operating voltage is as 3.3V, so the design of the voltage conversion circuit, the voltage from 5V to 3.3V conversion. Voltage conversion chips used in LT1587CM-3.3, the circuit connection as shown in Figure 7. In the design, the circuit added 2Amax fuse to prevent the currents too large to burn the circuit.
2.3 FPGA Module Design
FPGA module is the core of filter system, bearing all of the digital circuit part. In the design process, emphasizing the concept of system on chip, implemented on the FPGA platform, the system needed in all the digital logic, including adders, multipliers, buffers, PLL (Phase-locked Loop, PLL), USB interface logic. Allowing the number of parts of the system is fully programmable adjustable state, just update the FPGA program can be demand-driven and has strong adaptability and flexibility.