求助！！各位Verilog高手看壹看，這段代碼有沒有問題！！關於sram讀寫測試的。怎麽沒有sram使能信號啊

a. assign wr_rep=(delay==(5'd9999)); //9999 < 16384 = 14 bit, so 14'd9999 shall be correct.

b. always @(cstate or wr_rep or rd_rep or cnt) //sensitivity list does not cover all input variable

we: write enable, if you like to WRITE data into SRAM, put "we" as 1'b1

ce: chip enable, if you like to turn SRAM on (write or read it), put "ce" as 1'b1

oe: output enable, if you like SRAM output data, put "oe" as 1'b1, if set 1'b0 on "oe", then output will be high impedance.

let me know if you need more help.