output out;
input i0,i1,i2,....i31;
input s3,s2,s1,s0;
reg out;
always@(*)
begin
case({s3,s2,s1,s0})
4'b0000:out=i0;
4'b0001:out=i1;
.
4'b1111:out=i31;
default:out=1'bx;
end case
end
endmodule