library IEEE;
use IEEE.std_logic_1164.all;
entity choose_8_1 is
port( a,b,c,d,e,f,g,h : in std_logic_vector( 7 downto 0 );
choose : in std_logic_vector( 2 downto 0 );
Z : out std_logic_vector( 7 downto 0 ) );
end choose_8_1;
architecture Medied of choose_8_1 is
begin
process（choose）
begin
case choose is
when "000" => Z<=a;
when "001" => Z<=b;
when "010" => Z<=c;
when "011" => Z<=d;
when "100" => Z<=e;
when "101" => Z<=f;
when "110" => Z<=g;
when others => Z<=h;
end case;
end process;
end Medied;
希望妳以後自己多動手寫，安裝個Quartus II，自己學，進步很快的。
——Medied.Lee