VHDL 10分頻電路時鐘的程序 越簡單越好 能在Modelsim上仿真

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY fenpq IS

PORT ( CLK : IN STD_LOGIC; --輸入時鐘

CLK1 : OUT STD_LOGIC); --輸出時鐘

END fenpq; ARCHITECTURE behav OF fenpq IS

BEGIN

PROCESS (CLK)

VARIABLE ss,CLK11:STD_LOGIC_VECTOR(2 DOWNTO 0):="000";

BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF ss="101" THEN --計數

ss:="000";CLK11:=CLK11;

END IF;

END IF;

CLK1<=CLK11;

END PROCESS;

END behav;