VHDL編程設計題，設計壹個帶異步清零功能的8位累加器電路。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY accumulator IS

PORT (reset_n,clk: IN STD_LOGIC;

code_in: IN STD_LOGIC_VECTOR(7 DOWNTO 0);

sum_out: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));

END accumulator;

ARCHITECTURE ONE OF accumulator IS

SIGNAL sum:STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN

PROCESS(reset_n,clk)

BEGIN

? IF reset_n='0' THEN

? sum <= (OTHERS=>'0');

? ELSIF rising_edge(clk) THEN

? sum <= sum+code_in;

? END IF;

END PROCESS;

sum_out <= sum;

END ONE;

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