1、要有多種花型變化（至少設計4種）。
2、多種花型可以自動變換，循環往復。
3、彩燈變換的快慢節拍可以選擇。
4、具有清零開關。
系統設計方案
根據系統設計要求，現設計壹個具有六種花型循環變化的彩燈控制器。系統設計采用自頂向下的設計方法，系統的整體組轉設計原理圖如下圖所示，它由時序控制模塊和顯示控制模塊兩部分組成。整個系統有3個輸入信號：系統時鐘信號CLK，系統清零信號CLR和控制彩燈節奏快慢的選擇開關SPRRD。9個輸出信號LED[8..0]，分別用於模擬彩燈。
VHDL源程序
時序控制模塊的VHDL源程序（SX.VHD）
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY SX IS
PORT(
SPEED:IN STD_LOGIC;
CLK:IN STD_LOGIC;
CLR:IN STD_LOGIC;
CLK1:OUT STD_LOGIC);
END SX;
ARCHITECTURE ART OF SX IS
SIGNAL CK:STD_LOGIC;
BEGIN
PROCESS(CLK,CLR,SPEED)IS
VARIABLE TEMP:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
IF CLR='1' THEN
CK<='0';
TEMP:="000";
ELSIF(CLK'EVENT AND CLK='1')THEN
IF(SPEED='1')THEN
IF TEMP="001" THEN
TEMP:="000";
CK<=NOT CK;
ELSE TEMP:=TEMP+'1';
END IF;
ELSE
IF TEMP="111" THEN
TEMP:="000";
CK<=NOT CK;
ELSE
TEMP:=TEMP+'1';
END IF;
END IF;
END IF;
END PROCESS;
CLK1<=CK;
END ART;
顯示控制模塊的VHDL源程序（XS.VHD）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY XS IS
PORT(CLK1:IN STD_LOGIC;
CLR:IN STD_LOGIC;
LED:OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
END ENTITY XS;
ARCHITECTURE ART OF XS IS
TYPE STATE IS(S0,S1,S2,S3,S4,S5,S6);
SIGNAL CURRENT_STATE:STATE;
SIGNAL LIGHT:STD_LOGIC_VECTOR(8 DOWNTO 0);
BEGIN
PROCESS(CLR,CLK1)IS
CONSTANT L1:STD_LOGIC_VECTOR(8 DOWNTO 0):="001001001";
CONSTANT L2:STD_LOGIC_VECTOR(8 DOWNTO 0):="010010010";
CONSTANT L3:STD_LOGIC_VECTOR(8 DOWNTO 0):="011011011";
CONSTANT L4:STD_LOGIC_VECTOR(8 DOWNTO 0):="100100100";
CONSTANT L5:STD_LOGIC_VECTOR(8 DOWNTO 0):="101101101";
CONSTANT L6:STD_LOGIC_VECTOR(8 DOWNTO 0):="110110110";
BEGIN
IF CLR='1' THEN
CURRENT_STATE<=S0;
ELSIF(CLK1'EVENT AND CLK1='1')THEN
CASE CURRENT_STATE IS
WHEN S0=> LIGHT<="ZZZZZZZZZ"; CURRENT_STATE<=S1;
WHEN S1=> LIGHT<=L1; CURRENT_STATE<=S2;
WHEN S2=> LIGHT<=L2; CURRENT_STATE<=S3;
WHEN S3=> LIGHT<=L3; CURRENT_STATE<=S4;
WHEN S4=> LIGHT<=L4; CURRENT_STATE<=S5;
WHEN S5=> LIGHT<=L5; CURRENT_STATE<=S6;
WHEN S6=> LIGHT<=L6; CURRENT_STATE<=S1;
END CASE;
END IF;
END PROCESS;
LED<=LIGHT;
END ART;
彩燈控制器頂層設計的VJDL源程序（CAIDENG.VHD）
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CAIDENG IS
PORT(CLK:IN STD_LOGIC;
CLR:IN STD_LOGIC;
SPEED:IN STD_LOGIC;
LED:OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
END ENTITY;
ARCHITECTURE ART OF CAIDENG IS
COMPONENT SX IS
PORT(SPEED:IN STD_LOGIC;
CLK:IN STD_LOGIC;
CLR:IN STD_LOGIC;
CLK1:OUT STD_LOGIC);
END COMPONENT SX;
COMPONENT XS IS
PORT(CLK1:IN STD_LOGIC;
CLR:IN STD_LOGIC;
LED:OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
END COMPONENT XS;
SIGNAL S:STD_LOGIC;
BEGIN
U1:SX PORT MAP(SPEED,CLK,CLR,S);
U2:XS PORT MAP(S,CLR,LED);
END ART;