給予FPGA的RS編碼器的VHDL編程源代碼

RS編碼的乘法器：根據伽羅華域運算規則設計乘法器。當系數為0時，乘法器的Verilog HDL代碼如下：

module mula_0(a,c);

input [5:0] a;

output [5:0] c;

reg [5:0] c;

always @(a)

begin

c[5]<=a[5];

c[4]<=a[4];

c[3]<=a[3];

c[2]<=a[2];

c[1]<=a[1];

c[0]<=a[0];

end

endmodule

代碼分析：

由於伽羅華域的加法是作異或運算，當系數為0時，乘積即為本身。

當系數為1時，乘法器的Verilog HDL 代碼如下：

module mula_1(a,c);

input [5:0] a;

output [5:0] c;

reg [5:0] c;

always @(a)

begin

c[5]<=a[4];

c[4]<=a[3];

c[3]<=a[2];

c[2]<=a[1];

c[1]<=a[5] ^ a[0];

c[0]<=a[5];

end

endmodule

RS編碼的乘法器，設計Verilog HDL代碼如下：

module rscode(clk, clr, start, datavalid, x, y);

input clk;

input clr;

input start;

input datavalid;

input [5:0] x;

output [5:0] y;

reg [5:0] y;

wire [5:0] mul0, mul1, mul2, mul3, mul4, mul5;

wire [5:0] mul6, mul7, mul8, mul9, mul10, mul11;

wire [5:0] mul12, mul13, mul14, mul15, mul16, mul17;

reg [5:0] r0, r1, r2, r3, r4, r5;

reg [5:9] r6, r7, r8, r9, r10, r11;

reg [5:0] r12, r13, r14, r15, r16, r17;

reg [5:0] databack;

//調用乘法器

mula_45 g0(.a(databack), .c(mul0));

mula_48 g1(.a(databack), .c(mul1));

mula_3 g2(.a(databack), .c(mul2));

mula_51 g3(.a(databack), .c(mul3));

mula_35 g4(.a(databack), .c(mul4));

mula_11 g5(.a(databack), .c(mul5));

mula_32 g6(.a(databack), .c(mul6));

mula_59 g7(.a(databack), .c(mul7));

mula_25 g8(.a(databack), .c(mul8));

mula_31 g9(.a(databack), .c(mul9));

mula_6 g10(.a(databack), .c(mul10));

mula_21 g11(.a(databack), .c(mul11));

mula_38 g12(.a(databack), .c(mul12));

mula_61 g13(.a(databack), .c(mul13));

mula_3 g14(.a(databack), .c(mul14));

mula_0 g15(.a(databack), .c(mul15));

mula_59 g16(.a(databack), .c(mul16));

mula_22 g17(.a(databack), .c(mul17));

always @(posedge clk)

begin

if(clr == 1'b0)

begin

r0 <= 6'd0;

r1 <= 6'd0;

r2 <= 6'd0;

r3 <= 6'd0;

r4 <= 6'd0;

r5 <= 6'd0;

r6 <= 6'd0;

r7 <= 6'd0;

r8 <= 6'd0;

r9 <= 6'd0;

r10 <= 6'd0;

r11 <= 6'd0;

r12 <= 6'd0;

r13 <= 6'd0;

r14 <= 6'd0;

r15 <= 6'd0;

r16 <= 6'd0;

r17 <= 6'd0;

end

else if(start == 1'b1) //作異或運算

begin

r0 <= mul0;

r1 <= r0 ^ mul1;

r2 <= r1 ^ mul2;

r3 <= r2 ^ mul1;

r4 <= r3 ^ mul1;

r5 <= r4 ^ mul1;

r6 <= r5 ^ mul1;

r7 <= r6 ^ mul1;

r8 <= r7 ^ mul1;

r9 <= r8 ^ mul1;

r10 <= r9 ^ mul1;

r11 <= r10 ^ mul1;

r12 <= r11 ^ mul1;

r13 <= r12 ^ mul1;

r14 <= r13 ^ mul1;

r15 <= r14 ^ mul1;

r16 <= r15 ^ mul1;

r17 <= r16 ^ mul1;

end

end

always @(datavalid or x or r17)

begin

if(datavalid == 1'b1)

begin

databack <= x ^ r17;

end

else

begin

databack <= 6'd0;

end

end

always @(datavalid or x or r17)

begin

if(datavalid == 1'b1) //輸出數據

begin

y <= x;

end

else //輸出檢驗碼

begin

y <= r17;

end

end

endmodule